Sensor fault detection with low computational cost : a proposed neural network-based control scheme

The paper describes a low computational power method for detecting sensor faults. A typical fault detection unit for multiple sensor fault detection with modelbased approaches, requires a bank of estimators. The estimators can be either observer or artificial intelligence based. The proposed control scheme uses an artificial intelligence approach for the development of the fault detection unit abbreviated as ‘i-FD’. In contrast with the bank-estimators approach the proposed i-FD unit is using only one estimator for multiple sensor fault detection. The efficacy of the scheme is tested on an Electro-Magnetic Suspension (EMS) system and compared with a bank of Kalman estimators in simulation environment

AI-based actuator/sensor fault detection with low computational cost for industrial applications

A low computational cost method is proposed for detecting actuator/sensor faults. Typical model-based fault detection units for multiple sensor faults, require a bank of estimators (i.e., conventional Kalman estimators or artificial intelligence based ones). The proposed fault detection scheme uses an artificial intelligence approach for developing of a low computational power fault detection unit abbreviated as ‘iFD’. In contrast to the bank-of-estimators approach, the proposed iFD unit employs a single estimator for multiple actuator/sensor fault detection. The efficacy of the proposed fault detection scheme is illustrated through a rigorous analysis of the results for a number of sensor fault scenarios on an electromagnetic suspension system

Facilitating autonomous systems with AI-based fault tolerance and computational resource economy

Proposed is the facilitation of fault-tolerant capability in autonomous systems with particular consideration of low computational complexity and system interface devices (sensor/actuator) performance. Traditionally model-based fault-tolerant/detection units for multiple sensor faults in automation require a bank of estimators, normally Kalman-based ones. An AI-based control framework enabling low computational power fault tolerance is presented. Contrary to the bank-of-estimators approach, the proposed framework exhibits a single unit for multiple actuator/sensor fault detection. The efficacy of the proposed scheme is shown via rigorous analysis for several sensor fault scenarios for an electro-magnetic suspension testbed

Design architecture, implementation and application of intelligent control algorithms in digital VLSI systems

Διδακτορική Διατριβή--Εθνικό Μετσόβιο ΠολυτεχνείοSoftware implementations of intelligent control algorithms suffer slow execution time and increased resources demand. Referring to Genetic Algorithms, convergence to the optimal point can prove extremely time-consuming for hard or complex optimization problems, hence not allowing their use in real-time applications. Therefore, it is obvious that applying these algorithms, implemented in software, in real-time robotic applications is practically unfeasible. Based on the last fact, and the fast growth in digital circuit technology, a large number of research work dealing with intelligent control algorithms in programmable logic chips such as Field Programmable Gate Arrays or FPGAs, have been conducted and published over the last few years.The implementation of such algorithms in hardware, offers a substantial increase of data processing speed due to the inherent parallelism of the logic resources into the FPGA that allows for considerable computational throughput, thus rendering them capable of being used in real-time and increased computational complexity applications. Various intelligent algorithm cores can be easily combined with other core modules (e.g., microprocessor core) in order to form a System on a Chip (SoC), which it can be part of an autonomous robotic platform. Moreover, these cores could be used in future applications, thus increasing design re-usability. Finally, intelligent control algorithms implementation on FPGA devices helps to secure reduced power consumption, size, and cost, operation in harsh environments, and easy transfer to structured Application Specific Integrated Circuits (ASICs) if necessary. In this work, several new architectures for the design of intelligent control algorithms are proposed, specifically fuzzy controllers and genetic algorithm cores with the use of Hardware Description Languages (HDLs) and Electronic Design Automation (EDA) tools. In particular, the architectural design and implementation of a parameterized zero-order Takagi-Sugeno Digital Fuzzy Controller (DFLC) core that processes only the active rules is presented which achieves a high clock frequency. Thereinafter, a modified version of the DFLC is presented using a method that increases the parallelism of the architecture and achieves twice the data processing rate of the first core, by processing more than one active rule at the input of the controller per clock cycle. The fuzzy controller core was successfully bound with a microprocessor core and other secondary modules into a SoC to be eventually integrated in a robotic platform for path tracking problems. This SoC offers increased data processing and flexible hardware for different tasks. The SoC was embodied onto a Pioneer P3-DX8 mobile robot and several experiments were performed to evaluate the system’s overall performance. Finally in this work the design, implementation and performance evaluation of a Genetic Algorithm (GA) core is being analyzed. The GA core presented here possesses a high frequency of operation and logic design parallelism, allowing it to be effectively used in real-time applications. The core was evaluated using several benchmarking functions and solving the Travelling Salesman Problem (TSP) for a different number of cities

Implementation and testing of variable-time-delays-robust telemanipulation through master state prediction

Master Thesis--De Montfort UniversityThis project is based on the implementation and testing of variable-time-delays-robust telemanipulation through master state prediction by using high level languages (C++) and Matlab software package. Time delay compensation in teleoperation can be achieved by predicting the human arm position and force (effectively the master state). The method is based on the prediction of the master state (position xm and force fm) only, which can be much more simple and accurate than predicting the slave and the remote environment, and incorporates this in a stable force-feedback scheme. The telemanipulation method was split into its fundamental elements and implemented as a number of functions. Furthermore two different methods (interpolation, curve fitting theories) for implementing the predictor model were developed and tested. Finally, the telemanipulation method was simulated (using sinusoidal inputs as the neural input) several times and the results produced, were evaluated. Due to time limitations and programming difficulties, the programming of the force feedback joystick (role of master robot) was not included

Digit-Serial IIR Filter Implementation on FPGA

Bsc--De Montfort UnivercityThis project is based on the implementation of a digit-serial Iffi filter, on FPGA by either using VHDL or ECAD programs (Viewlogic). The application of the digit-serial structures to the design of IIR filters introduces delay elements in the feed back loop of the HR filter. This offers the possibility of pipelining the feed back loop inherent in the HR filters. The digit serial structure is based on the feed forward of the carry digit, which allows sub digit pipelining to increase the throughput rate ofthe HR filters. The implementation of the digital filter was split into its fundamental elements according to its block diagram. All the elements ofthe filter were designed, simulated and tested to prove their functionality. Furthermore a 1st order digit-serial HR filter (n=4, M=32) was composed and simulated to prove that is functioning satisfactorily. Finally the last should be downloaded onto the FPGA and tested. The FPGA chip, which was available at the time of this project, was located on a general use board intended for less complex designs. Due to this fact the 1st order digit-serial filter was not downloaded, but the 16x16 bit digit-serial multiplier with digit-serial adder and parallel-in to serial-out register was downloaded instead and tested

Design paradigms of intelligent control systems on a chip

This paper focuses on the Field Programmable Gate Array (FPGA) design and implementation of intelligent control system applications on a chip, specifically fuzzy logic and genetic algorithm processing units. Initially, an overview of the FPGA technology is presented, followed by design methodologies, development tools and the use of hardware description languages (HDL). Two FPGA design examples with the use of Hardware Description Languages (HDLs) of parameterized fuzzy logic controller cores are discussed. Thereinafter, a System-on-a-Chip (SoC) designed by the authors in previous work and realized on FPGA featuring a Digital Fuzzy Logic Controller (DFLC) and a soft processor core for the path tracking problem of mobile robots is discussed. Finally a Genetic Algorithm implementation (previously published by the authors) in FPGA chip for the Traveling Salesman Problem (TSP) is also discussed

A parameterized T-S digital fuzzy logic processor: soft core VLSI design and FPGA implementation

Fuzzy Logic (FL) was developed by Zadeh to deal with the uncertainty involved in decision making and system modeling and control of real–life systems, and is an extension of the two–valued logic defined by the binary pair {false, true} or {0,1} to the entire continuous interval [0,1] of logic values between false=0 and true=1. The purpose of this paper is to design and implement a zero-order Takagi-Sugeno (T-S) parameterized digital fuzzy logic processor (DFLP), in which only the active rules (i.e. rules that give a non–null contribution for a given data set) are considered, at high speed of operation, without significant increase in hardware complexity. The DFLP discussed in this paper achieves an internal core processing speed of at least 100 MHz, and based on the chosen parameters is featuring four 12-bit inputs and one 12-bit output, with seven trapezoidal shape membership functions per input and a rule base of up to 2401 rules. The proposed architecture was implemented in a Field Programmable Gate Array (FPGA) chip with the use of a very high-speed integrated-circuit hardware-description-language (VHDL) and advanced synthesis and place and route tools

On the issue of LQG embedded control realization in a Maglev system

Sensor selection in control design receives substantial interest in the last few years. We disseminate work on Field Programmable Gate Array (FPGA)-based embedded software platform validating a systematic sensor selection framework and target efficient FPGA resource allocation. Sensor selection combines multi-objective optimization, Linear-Quadratic-Gaussian (LQG) control, applied to a Maglev suspension. The nonlinear Maglev model is realized on software platform forming a Hardware-in-the-loop (HIL) as an economic and reliable validation platform for the design setup. The LQG controller was modeled in fixed point, described in Verilog Hardware Description Language (HDL) and tied up with an ethernet core to form an FPGA-in-the-loop system prior to logic synthesis and FPGA place and route. The results illustrate efficient FPGA resource allocation level pertinent to extending to a core sensor fault tolerant scheme

A parameterized genetic algorithm ip core design and implementation

Genetic Algorithm (GA) is a directed random search technique working on a population of solutions and based on natural selection. However, its convergence to the optimum may be very slow for complex optimization problems, especially when the GA is software implemented, making it difficult to be used in real time applications. In this paper a parameterized GA Intellectual Property (IP) core is designed and implemented on hardware, achieving impressive time-speedups when compared to its software version. The parameterization stands for the number of population individuals and their bit resolution, the bit resolution of each individual's fitness, the number of elite genes in each generation, the crossover and mutation methods, the maximum number of generations, the mutation probability and its bit resolution. The proposed architecture is implemented in a Field Programmable Gate Array Chip (FPGA) with the use of a Very-HighSpeed Integrated Circuits Hardware Description Language (VHDL) and advanced synthesis and place and route tools. The GA discussed in this work achieves a frequency rate of 92 MIIz and is evaluated using the Traveling Salesman Problem (TSP) as well as several benchmarking functions